/*--------------------------------------------------------------------------*/ /* A9101.H */ /* */ /* Header file for A9101 RF SoC microcontroller. */ /* Copyright (c) 2017 AMICCOM Electronics Corp. */ /* */ /* All rights reserved. */ /*--------------------------------------------------------------------------*/ #ifndef __A9101_H__ #define __A9101_H__ //-------------------------------------------------------------------------- // 8051 SFR //-------------------------------------------------------------------------- /* BYTE Registers */ sfr P0 = 0x80; sfr P1 = 0x90; sfr P2 = 0xA0; sfr P3 = 0xB0; sfr PSW = 0xD0; sfr ACC = 0xE0; sfr B = 0xF0; sfr SP = 0x81; sfr DPL = 0x82; sfr DPH = 0x83; sfr DPL1 = 0x84; sfr DPH1 = 0x85; sfr PCON = 0x87; sfr TCON = 0x88; sfr TMOD = 0x89; sfr TL0 = 0x8A; sfr TL1 = 0x8B; sfr TH0 = 0x8C; sfr TH1 = 0x8D; sfr CKCON = 0x8E; sfr EIF = 0x91; sfr SCON = 0x98; sfr SBUF = 0x99; sfr FLASHCTRL = 0x9A; sfr FLASHTMR = 0x9B; sfr IE = 0xA8; sfr PWM0CON = 0xA9; sfr PWM0H = 0xAA; sfr PWM0L = 0xAB; sfr PWM1CON = 0xB1; sfr PWM1H = 0xB2; sfr PWM1L = 0xB3; sfr IP = 0xB8; sfr PCONE = 0xB9; sfr RSFLAG = 0xBA; sfr IOSEL = 0xBB; sfr IOSEL2 = 0xBC; sfr T2CON = 0xC8; sfr T2IF = 0xC9; sfr RCAP2L = 0xCA; sfr RCAP2H = 0xCB; sfr TL2 = 0xCC; sfr TH2 = 0xCD; sfr WDCON = 0xD8; sfr EIE = 0xE8; sfr TA = 0xEB; sfr SPCR = 0xEC; sfr SPSR = 0xED; sfr SPDR = 0xEE; sfr SSCR = 0xEF; sfr I2CSADR = 0xF1; sfr I2CSCR = 0xF2; sfr I2CSBUF = 0xF3; sfr I2CMSA = 0xF4; sfr I2CMCR = 0xF5; sfr I2CMBUF = 0xF6; sfr I2CMTP = 0xF7; sfr EIP = 0xF8; sfr P0OE = 0xD1; sfr P0PUN = 0xD2; sfr P0WUN = 0xD3; sfr P1OE = 0xD9; sfr P1PUN = 0xDA; sfr P1WUN = 0xDB; sfr P2OE = 0xA1; sfr P2PUN = 0xA2; sfr P2WUN = 0xA3; sfr P3OE = 0xE1; sfr P3PUN = 0xE2; sfr P3WUN = 0xE3; /* BIT Registers */ sbit ERFINT = EIE^3; sbit EWDI = EIE^5; sbit PWDI = EIP^5; /* PSW */ sbit CY = PSW^7; sbit AC = PSW^6; sbit F0 = PSW^5; sbit RS1 = PSW^4; sbit RS0 = PSW^3; sbit OV = PSW^2; sbit P = PSW^0; /* TCON */ sbit TF1 = TCON^7; sbit TR1 = TCON^6; sbit TF0 = TCON^5; sbit TR0 = TCON^4; sbit IE1 = TCON^3; sbit IT1 = TCON^2; sbit IE0 = TCON^1; sbit IT0 = TCON^0; /* IE */ sbit EA = IE^7; sbit ET2 = IE^5; sbit ES = IE^4; sbit ET1 = IE^3; sbit EX1 = IE^2; sbit ET0 = IE^1; sbit EX0 = IE^0; /* IP */ sbit PT2 = IP^5; sbit PS = IP^4; sbit PT1 = IP^3; sbit PX1 = IP^2; sbit PT0 = IP^1; sbit PX0 = IP^0; /* P3 */ sbit RD = P3^7; sbit WR = P3^6; sbit T1 = P3^5; sbit T0 = P3^4; sbit INT1 = P3^3; sbit INT0 = P3^2; sbit TXD = P3^1; sbit RXD = P3^0; /* SCON */ sbit SM0 = SCON^7; sbit SM1 = SCON^6; sbit SM2 = SCON^5; sbit REN = SCON^4; sbit TB8 = SCON^3; sbit RB8 = SCON^2; sbit TI = SCON^1; sbit RI = SCON^0; /* P1 */ sbit T2EX = P1^1; sbit T2 = P1^0; /* T2CON */ sbit TF2 = T2CON^7; sbit EXF2 = T2CON^6; sbit RCLK = T2CON^5; sbit TCLK = T2CON^4; sbit EXEN2 = T2CON^3; sbit TR2 = T2CON^2; sbit C_T2 = T2CON^1; sbit CP_RL2 = T2CON^0; /* P0 */ sbit P0_7 = P0^7; sbit P0_6 = P0^6; sbit P0_5 = P0^5; sbit P0_4 = P0^4; sbit P0_3 = P0^3; sbit P0_2 = P0^2; sbit P0_1 = P0^1; sbit P0_0 = P0^0; /* P1 */ sbit P1_7 = P1^7; sbit P1_6 = P1^6; sbit P1_5 = P1^5; sbit P1_4 = P1^4; sbit P1_3 = P1^3; sbit P1_2 = P1^2; sbit P1_1 = P1^1; sbit P1_0 = P1^0; /* P2 */ sbit P2_7 = P2^7; sbit P2_6 = P2^6; sbit P2_5 = P2^5; sbit P2_4 = P2^4; sbit P2_3 = P2^3; sbit P2_2 = P2^2; sbit P2_1 = P2^1; sbit P2_0 = P2^0; /* P3 */ sbit P3_7 = P3^7; sbit P3_6 = P3^6; sbit P3_5 = P3^5; sbit P3_4 = P3^4; sbit P3_3 = P3^3; sbit P3_2 = P3^2; sbit P3_1 = P3^1; sbit P3_0 = P3^0; //-------------------------------------------------------------------------- // RF Register //-------------------------------------------------------------------------- #define CONFIG 0x0800 #define MODE_REG 0x0800 #define MODEC1_REG 0x0801 #define MODEC2_REG 0x0802 #define CALC_REG 0x0803 #define FIFO1_REG 0x0804 #define FIFO2_REG 0x0805 #define Clock_REG 0x0806 #define VCB_REG 0x0807 #define RCOSC3_REG 0x0808 #define CKO_REG 0x0809 #define GIO1_REG 0x080A #define GIO2_REG 0x080B #define DATARATECLK_REG 0x080C #define PLL1_REG 0x080D #define PLL2_REG 0x080E #define PLL3_REG 0x080F #define PLL4_REG 0x0810 #define PLL5_REG 0x0811 #define CHGROUP1_REG 0x0812 #define CHGROUP2_REG 0x0813 #define TX1_REG 0x0814 #define TX2_REG 0x0815 #define DELAY1_REG 0x0816 #define DELAY2_REG 0x0817 #define RX_REG 0x0818 #define RXGAIN1_REG 0x0819 #define RXGAIN2_REG 0x081A #define RXGAIN3_REG 0x081B #define RXGAIN4_REG 0x081C #define RSSI_REG 0x081D #define ADC_REG 0x081E #define CODE1_REG 0x081F #define CODE2_REG 0x0820 #define CODE3_REG 0x0821 #define IFCAL1_REG 0x0822 #define IFCAL2_REG 0x0823 #define VCOC_REG 0x0824 #define VCOBAND1_REG 0x0825 #define VCOBAND2_REG 0x0826 #define VCODEV1_REG 0x0827 #define VCODEV2_REG 0x0828 #define VCODEV3_REG 0x0829 #define VCOMODDELAY_REG 0x082A #define BATTERY_REG 0x082B #define TXTEST_REG 0x082C #define RXDEM1_REG 0x082D #define RXDEM2_REG 0x082E #define CPC1_REG 0x082F #define CPC2_REG 0x0830 #define CRYSTAL_REG 0x0831 #define PLLTEST_REG 0x0832 #define VCOTEST_REG 0x0833 #define RFANALOG_REG 0x0834 #define IFAT_REG 0x0835 #define CHSELECT_REG 0x0836 #define VRB_REG 0x0837 #define DataRate_REG 0x0838 #define FCR_REG 0x0839 #define ARD_REG 0x083A #define AFEP_REG 0x083B #define WMUX_REG 0x083C #define FCB0_REG 0x083D #define FCB1_REG 0x083E #define FCB2_REG 0x083F #define FCB3_REG 0x0840 #define ID7_REG 0x0841 #define ID6_REG 0x0842 #define ID5_REG 0x0843 #define ID4_REG 0x0844 #define ID3_REG 0x0845 #define ID2_REG 0x0846 #define ID1_REG 0x0847 #define ID0_REG 0x0848 #define DID0_REG 0x0849 #define DID1_REG 0x084A #define DID2_REG 0x084B #define DID3_REG 0x084C #define ADCCTL_REG 0x084D #define ADCAVG1_REG 0x084E #define ADCAVG2_REG 0x084F #define ADCAVG3_REG 0x0850 #define TMRINV_REG 0x0851 #define TMRCTL_REG 0x0852 #define EXT1_REG 0x0853 #define EXT2_REG 0x0854 #define EXT3_REG 0x0855 #define EXT4_REG 0x0856 #define EXT5_REG 0x0857 #define PWRCTL_REG 0x0858 #define INTSW_REG 0x0859 #define RCOSC4_REG 0x085A #define RCOSC5_REG 0x085B #define RCOSC6_REG 0x085C #define RCOSC7_REG 0x085D #define RCOSC8_REG 0x085E #define RTC_REG 0x085F #define AGC1_REG 0x0860 #define AGC2_REG 0x0861 #define AGC3_REG 0x0862 #define FLASH_REG 0x0863 #define RCOSC1_REG 0x0864 #define RCOSC2_REG 0x0865 #define WOR_REG 0x0866 #define TCODE_REG 0x0867 #define SYNCS_REG 0x0868 #define CTR_REG 0x0869 #define RCKS_REG 0x086A #define DET_REG 0x086B #define DC_REG 0x086C #define PRE_REG 0x086D #define PA_REG 0x086E #define INTF_REG 0x086F #define TX3_REG 0x0870 #define TCKG0_REG 0x0871 #define TCKG1_REG 0x0872 #define TX_FIFO 0x0900 // 0x0900~0x097F = 128 bytes #define RX_FIFO 0x0980 // 0x0980~0x09FF = 128 bytes #define ANACTL_REG 0x0A00 #define AGCCAL_REG 0x0A01 #define AMP_REG 0x0A02 #define PKCAL_REG 0x0A03 #define OSCAL1_REG 0x0A04 #define OSCAL2_REG 0x0A05 #define ADCDLY_REG 0x0A06 #define VOL_REG 0x0A08 #define SRSEL_REG 0x0A09 #define STATE_REG 0x0A0A #define ADCRB_REG 0x0A0B #define DACWB_REG 0x0A0C #define EFFCTL_REG 0x0A0D #define CODECTL_REG 0x0A0E #define TESTMODE_REG 0x0A0F #define FSTEPL_REG 0x0A10 #define FSTEPH_REG 0x0A11 //-------------------------------------------------------------------------- // Strobe and Reset Command //-------------------------------------------------------------------------- /* RF Strobe command */ #define CMD_SLEEP 0x80 // SLEEP mode #define CMD_IDLE 0x90 // IDLE mode #define CMD_STBY 0xA0 // Standby mode #define CMD_PLL 0xB0 // PLL mode #define CMD_RX 0xC0 // RX mode #define CMD_TX 0xD0 // TX mode /* RF Reset command */ #define RF_RST 0x80 //RF reset #define TXPOINT_RST 0x40 //TX FIFO address pointrt reset #define RXPOINT_RST 0x20 //RX FIFO address pointer reset #define FIFOORN 0x08 //FIFO buffer clear #endif